The difficult part is the place and route algorithm, not the bitstream. The proprietary ones already take quite a long time to solve: I regularly have 12-24h runs. Perhaps an open source one could do better? But it's not quite as straightforward as reverse engineering a proprietary bitstream.
When I first started doing chip design my boss paid more for tools per year than he paid me ... now days open source tool chains are leaping ahead ... I don't need a boss (or VCs) in order to design chips
Somewhere in reverse-engineering-land is the desire to figure out undocumented hardware blocks. I’m not disagreeing about PNR here.
I have to admit that I haven't looked too closely into this but my understanding is that place & route is essentially an NP hard optimization problem. Would it be possible to translate this into a SAT problem and solve it with a state of the art SAT solver?
That's why nextpnr exists :)
https://github.com/YosysHQ/nextpnr
As someone actively working on nextpnr support for a fairly new FPGA architecture, it really is amazing that we have something like that in the open source world.
YosysHQ are one of my favorite companies to exist.