alt Hacker News> Are you seriously suggesting hobbyists should tapeout an ASIC instead of use an FPGA?
No. I said the low-end of FPGA sales is getting eaten by microcontrollers and the high-end of FPGAs sales is probably about to get eaten by custom ASICs.
Although the cost of making an ASIC is high, in the larger nodes it's not that high, and getting ever cheaper at FPGA performance levels and logic densities. FPGAs are terribly inefficient with their HW they're very easy to beat with an ASIC. They only get away with it because the NRE today is lower. But it's not an order of magnitude lower and I'm not sure how much longer that will be the case in nodes at 28nm and larger based on what I know Universities pay in tape-out classes.
Will there be very low qty projects where the NRE of developing an ASIC overwhelms that of an ASIC, sure. But will there be enough business in that niche to sustain the business of AMD, Intel and Lattice? Not obvious.
And I don't think the FPGA hobbyist market of people who "want to learn HDL" spends enough money to affect what's coming and this decision from AMD reflects that.
> 1. For one-off designs (quantity=1) ASICs will never beat a high end FPGA on unit price.
Never say never. These guys were able to convince investors you're wrong about that. :)
P.S. If you're a hobbyist who wants to make an ASIC... https://www.tinytapeout.com