That's really neat. TIL.

So the way this works seems to be this: It's an SRAM and an EEPROM in one little package along with a controller that talks with each, with a little capacitor (this clock uses 4.7uf) placed nearby.

The SRAM part does all of the normal SRAM stuff: It doesn't wear out from reading/writing, and as long as it has power it retains the data it holds.

The EEPROM does all the normal EEPROM stuff: It stores data forever (on the timescale of an individual human, anyway), but has somewhat-limited write cycles.

The controller: When it detects a low voltage, it goes "oh shit!" and immediately dumps the contents of the SRAM into EEPROM. This saves on EEPROM write cycles: If there are no power events, the EEPROM is never written at all.

Meanwhile, the capacitor: It provides the power for the chip to perform this EEPROM write when an "oh shit!" event occurs.

When power comes back, the EEPROM's data is copied back to SRAM.

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Downsides? This 47L04 only holds 4 kilobits. Upsides? For hobbyist projects and limited production runs, spending $1 to solve a problem is ~nothing. :)