alt Hacker NewsOne interesting observation is that successful RISC CPUs dont have a super simple ISA anymore. At least not in the frontend.
MIPS was notorious for having a simple ISA and RISCV is trying to mimick that to some extent. But look at thumb2 for example and you will see complex encodings and even variable instruction width.
Back in the day, Alpha and HPPA were commonly used as examples of 'with all this extra stuff is it still RISC?'. These days, I think the CISC/RISC divide is largely an historical artifact.