As TFA says, they are running the algorithm multiple times and they check that the results match, to guard against transient errors caused by radiation.

The permanent errors caused by radiation must be identified by periodic self tests. When the permanent damage is in a redundant structure, e.g. as mentioned in TFA when they find some memory bits that are permanently damaged, they must avoid using what is damaged.

Eventually radiation will destroy something that is essential, but until then the Snapdragon CPU should be usable.

Yeah, that's kind of awesome, isn't it?

Flying a helicopter on Mars was inspiring and useful for scouting, etc. But maybe the best thing coming out of it is undeniable proof that off-the-shelf hardware without radiation hardening is perfectly viable on Mars if you can just reboot it fast enough

It looks like the FPGA that monitors/controls the redundant/lockstep CPUs might be radiation tolerant. From [0]:

"..the critical FPGA which is always on for the duration of the mission, the radiation tolerant ProASIC3 is chosen with the military temperature grade (-55 C to 125 C) and -1 speed grade to mitigate the degradation in the propagation delay caused by the total dose radiation. The single-event upset (SEU) is mitigated with triple module redundancy (TMR) in the FPGA design.

...

The FPGA device is a military-grade version of MicroSemi’s ProASIC3L, which uses the same silicon as the radiation-tolerant device from the same family."[0]

The specs from [1] say there is also a specific radiation-tolerant variant.

So it looks like the CPUs themselves have dual lock-stepped cores, and the CPU checks for errors each cycle. If there's an error it flags the FPGA, which switches to the other CPU.

[0] https://rotorcraft.arc.nasa.gov/Publications/files/Balaram_A...

[1] https://ww1.microchip.com/downloads/aemDocuments/documents/F...