alt Hacker NewsI wonder if this kind of architecture would be fun to build an L4 microkernel based system with.
Context switching and message passing (synchronous anyway) are the same thing when you consider how rendezvous works.
BLWP instructions seem like this was “meant to be”.
the BLWP (Branch and Load Workspace Pointer) instruction essentially does a hardware context switch in two memory accesses -- it swaps the whole register set by changing a pointer, not copying. for a microkernel doing lots of IPC, that's a nice primitive. the 9900 predates L4 by two decades but the workspace design maps well to the message-passing model.