The C1 Ultra looks really powerful. 128 kb L1D cache on it's own is a ~10% IPC improvement that should let it pull firmly ahead of the x86 competition which is very stuck at 32kb due to the legacy 4k page size.
I'm sorry, I'm clearly missing something but why would page size impact L1 cache size?
I'm sorry, I'm clearly missing something but why would page size impact L1 cache size?