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cwzwarichtoday at 3:39 AM1 replyview on HN

https://github.com/coreboot/coreboot/blob/main/src/soc/intel...


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wmftoday at 4:16 AM

Context: Early in the firmware boot process the memory controller isn't configured yet so the firmware uses the cache as RAM. In this mode cache lines are never evicted since there's no memory to evict them to.

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