It does not. For any of the dual CCD parts AMD has ever released for consumers. Even Strix Halo which has higher bandwidth, lower latency interconnect doesn't make a single L3 across CCDs.

It'll probably only happen when they have a singular, large die filled with cache upon which both CCDs are stacked.

Run this test if you're curious: https://github.com/ChipsandCheese/MemoryLatencyTest

On a regular CCD:

32768,46.115

65536,74.243

98304,85.699

131072,91.42

262144,99.402

On a 3D cache CCD:

32768,11.992

65536,12.712

98304,29.921

131072,49.91

262144,86.059