Aegis – open-source FPGA silicon

The gap this closes is real. IceStorm and Apicula gave you open tooling but you were still loading bitstreams onto someone else's closed fabric. Yosys/nextpnr same story. Aegis is the first time the fabric itself is auditable, which matters a lot for anyone building hardware that needs a complete trust chain from RTL down to GDS. The wafer.space + open PDK path makes it actually tapeout-able, not just a simulation exercise. Curious how the LUT4 fabric competes on density against GF180 commercial offerings, that's usually where open implementations get humbling

As someone who has only dabbled with FPGAs before, this is incredible to see all the steps end-to-end for silicon development! I feel like the articles I've read always leave out details in one part or another, so it's interesting to see all the nix dependencies and build steps.

We make an asynchronous sea of gates runtime reconfigurable gate array chip very different from FPGA's but with the same use cases https://github.com/fiberhood/MorphleLogic/blob/main/README_M...

The problem is you can make test chips like Aegis for around $10 (depending on the yield, on how many of the first 1000 chips actually work) but they are just that, test chips.

In the case of Morphle Logic we make wafer scale integrations (WSI) with 10 billion transistors at 180nm for $750. That yields around 300 million 'gates', the largest commercial FPGA's barely get to 3 million. So our Morphle Logic WSI is the largest and fastest (up to 12 Ghz) FPGA you could get if we can find a few hundred buyers who want to pay up front (crowdfunding). Please email me if you are interested in such a enormous fast FPGA.

I'll buy an Aegis FPGFA test chip just to find out how hard it is to test a test chip.

Good luck RossComputerGuy, I hope you get working chips back. The same fab and supplier lost our first taped-out chips in the mail... and then they went bankrupt.

There's also an open source Authenticator software with the same name.

Neat project - there are already a couple of good open FPGA projects. Have a look at Dirk Koch's and the FABolous teams work. They are doing exceptional work.

But all open FPGA projects miss the IO required for a good design. They do not have any serdes hardware nor DDR IO cells.

Excellent. Put me down for a couple.