It's easy to mock in hindsight, but the failure mode isn't lack of imagination. It's extrapolating linearly from physical limits that were real at the time. In 1989, DRAM refresh cycles and bus bandwidth genuinely were bottlenecks that seemed fundamental. What nobody predicted was that the industry would sidestep those walls entirely (caches, pipelines, out-of-order execution, then multicore). Architectural innovation tends to appear orthogonally to wherever the current wall is.