A few thoughts:

> the complexity of some instructions (e.g. DJNZ)

Well, of course the idea of DJNZ was to implement a very common pattern (decrement a register and jump (normally backwards) if the result was not zero) - this tended to simplify code rather than make it more complex.

> However I couldn't keep all instructions and timings in my head.

I was never really interested in the timings, but I did get to the stage (not by conscious memorisation) of being able to assemble and disassemble Z80 code in my head, with some accuracy.

> I preferred, however, the fact that I/O was memory mapped on the 6502.

Many (most?) Z80 systems used memory mapped I/O. It's down to the hardware designer.

> Speedwise the 1MHz 6502 and 4MHz Z80 were on par.

This is a bit of an exaggeration, the 6502 was efficient but not that efficient. While generally understood that the Z80 took 2x-4x ticks to execute instructions as the 6502, in the real world its larger register set meant properly-written Z80 code could avoid expensive, slow round trips to memory.

Outside of artificial benchmarks real world performance shows that the 6502 is roughly 2x as efficient per clock cycle as the Z80[0], i.e. a 1 MHz 6502 is approximately equivalent to a 2 Mhz Z80.

This is reflected in the computers of the day, i.e. TRS-80s were not being blown out of the water by Commodore PETs.

[0] https://github.com/soegaard/minipascal/blob/master/minipasca...

> I preferred, however, the fact that I/O was memory mapped on the 6502.

The Z80 could do memory mapped IO as well of course (used at least in some arcade machines), but why waste valuable address space when there's an entire 64 KB of extra address space reserved for IO ;)