Same, I built a correctly-working AND gate made only of NAND gates but the tests don't pass.
The SR latch logic is also incorrect. Cross-coupled NORs had to be configured illogically to actually pass the tests and output correctly.
Also, the later puzzles (starting with memory) don't have any real tests. Seems like it just doesn't really exist past that point.
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The SR latch logic is also incorrect. Cross-coupled NORs had to be configured illogically to actually pass the tests and output correctly.
Also, the later puzzles (starting with memory) don't have any real tests. Seems like it just doesn't really exist past that point.