alt Hacker NewsGetting a logic-gate-level netlist from a GDS is trivial with industry standard chip design tools. Circuit designers do this every day. The hardest part will be reverse engineering the functionality.
I wish I had more time and I'd throw Calibre at it.
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Taniwha • today at 12:14 AM
It's even easier in this case because they've included the original verilog source ....
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Indeed, this is a problem for an energetic student who has free access to every tool in the Cadence, Synopsys, and Mentor portfolios: take the GDS-II layout, run it through extraction, generate a netlist, convert to higher-level blocks ("netlist-to-gate recovery"), translate to RTL HDL, then attempt to work out "what it does."
This is just a job posting in disguise for Jane Street: solve the puzzle, get a call from one of their recruiters.