alt Hacker News> HBM3E consumes approximately three times the wafer supply as D5 to produce a given number of bits in the same technology node
That's really interesting, and I wonder why? I believe HBM has redundant ECC bits by default, which would add a few %, but other than that, is it just that the yield is much lower due to die stacking? Of course, this is a 2024 document so things may have changed a bit since.
HBM requires stacking the chips. So they need to shave the layers, glue, stack more, shave again. They also require a substrate what is even more wafers. The issue is that a error in the stack means a lot of losses.
In order to get high bandwidth, you want memory as close as possible to the GPU. The more trace lane length = signal loss, bandwidth loss.. HBM is compact, and so you can stack 24GB modules, 8 around a GPU die.
If you tried to do that with normal memory, you need like 64 modules. So a a TON of traces more that all need to be equal length, and because so many = far away from the GPU = less bandwidth.
The issue is like stated above, its a process that waste a ton of wafers. Wafers that can make easily 3x more normal memory.
Intel with "Crescent Island" is trying to make a 160GB card using LPDDR5x memory but the bandwidth is only ~700GB/s.