The RISC-V specs insist that this is important for simplifying high performance designs, because a flag register is a single piece of shared state that instructions are constantly (and often inadvertently!) touching. This necessarily introduces hazards and serialization.
I don’t know enough about high performance microarchitecture design to evaluate that argument confidently, but it seems to make sense to me.
alt Hacker News
The RISC-V specs insist that this is important for simplifying high performance designs, because a flag register is a single piece of shared state that instructions are constantly (and often inadvertently!) touching. This necessarily introduces hazards and serialization.
I don’t know enough about high performance microarchitecture design to evaluate that argument confidently, but it seems to make sense to me.