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MBCooktoday at 4:26 AM1 replyview on HN

So in this specific case, if I understood correctly, here’s what should happen:

Interrupt(?) fires to trigger hypervisor, hypervisor figures out what it needs to do, jumps to that code, does its job, returns.

The “figured out what it needs to do” is the issue right? So what was actually happening was:

Same start… CPU predicts what hypervisor will do, speculatively loads instructions from mispredicted branch target, that wrong instruction reads memory(?) against the “no data prefetch” settings for that part of memory, CPU blows up/halts/whatever.

The fix is to mark the area the branch was mispredicted to in such a way that the CPU won’t prefetch instructions. Thus that won’t be run and prefetch data, thus no violation. CPU execution continues taking the correct branch and everything is fine.


Replies

sleirsgoevytoday at 10:23 AM

No, that instruction does not read memory. That instruction is itself IN the inaccessible memory.

It does not really matter how execution ended up in the HV in the first place. The misprediction happens due to having a branch-to-register instruction.