Recent generations of DRAM have barely shrunk feature sizes. DRAM hit the scaling wall before logic exactly because you cannot physically make capacitors much smaller without losing the charge faster and driving up the amount of time spent [wasted] on refresh. The only reason newer DDR standards are "faster" is that they have:

    1. increased the frequency of the interface (mostly in the phy / logic part of a DRAM)
    2. increased the number of banks within a single die
    3. split the 64 bit channel on a single DIMM into 2 x independent 32 bit channels

Of those, (1) benefits somewhat from a die shrink. (2) doesn't need smaller features, and (3) is completely orthogonal to die shrinks since it's entirely contained in the PCB design.

(1) is the biggest problem for DRAM performance scaling, and that's because the legacy of DIMMs is awful from a signal integrity perspective. As signals go above 10Gbps/pin, the length of stubs begin to impact signal integrity, and traditional DIMM sockets have pins going all the way through a motherboard. This is why LPCAMM and LPCAMM2 exist: to improve signal integrity, but LPCAMM2 is not yet widely adopted on desktops and servers.

FYI: DDR5 wasted logic on DRAM for latency increasing crappy on-die ECC (Error Checking and Correcting) because DRAM vendors are unwilling to make the correct engineering trade-offs to build reliable DRAM. As DRAM processes are not exactly great for logic, this makes little sense to me as I am a firm believer that DRAM should stick to being memory and let the memory controller and CPU / GPU vendor implement ECC instead of allowing DRAM to lie about how reliable it is.

If you really want to improve DRAM performance, do what the Chinese fabs are doing: build layers. Making use of the third dimension reduces wire length, lets DRAM manufacturers use larger capacitors resulting in higher reliability and reduced refresh frequency. Layers have been used in flash production for more than a decade now, and due to trade restrictions on EUV fabs, China has been pursuing 3D scaling aggressively. There is no reason that DRAM stacking should be limited to HBM attached to specialty SKUs of FPGAs and GPUs.

Speaking of HBM, HBM takes the approach of using a very wide bus (1024+ bits) at a much lower clock speed tp achieve high bandwidths (which makes maintaining signal integrity a lot easier). With LPCAMM style DRAM modules, increasing the width of DRAM busses becomes much less daunting compared to DIMM style PCB modules.

So, no, I don't think that increasing cell sizes in DRAM is a major pain for DRAM manufacturers. I think it's time that the customers speak up and refuse to accept marginal failure prone DRAM chips from vendors that value profit over a solidly engineered product.

[Side note: several papers have mentioned that not all DRAM manufacturers are vulnerable to rowhammer attacks.]