Visualizing the ARM64 Instruction Set (2024)

On the tangential question in the post:

"The specification describes bits as combinations of 0, 1, and x, but also sometimes includes (0) and (1). I’m not sure what the parenthesized versions mean"

the answer is that the (0) and (1) are should-be-zero and should-be-one bits: if you set them wrongly then you get CONSTRAINED UNPREDICTABLE behaviour where the CPU might UNDEF, NOP, ignore that you set the bit wrongly, or set the destination register to garbage. In contrast, plain 0 and 1 are bits that have to be that way to decode to this instruction, and if you set them to something else then the decode will take you to some other instruction (or to UNDEF) instead.

One interesting observation is that successful RISC CPUs dont have a super simple ISA anymore. At least not in the frontend.

MIPS was notorious for having a simple ISA and RISCV is trying to mimick that to some extent. But look at thumb2 for example and you will see complex encodings and even variable instruction width.

Cool idea, and agree with this sentence in the final paragraph

> It would be cool to make a similar visualization for RISC-V and compare it with ARM64.

Or even compare a subset of the instruction set to see what's missing on different archs.

For x86 there is sandpile.org, the probably densest human representation of the ISA, especially when it comes to the opcode tables.

Is there something comparable for ARM64? Basically, a landing page from which everything is just one click away, plus scrolling or a quick Ctrl-F search.

This would make for a neat poster.

So much empty space in the ISA.

can someone do the same for RISC5?