alt Hacker NewsGPT-Synopsys: Frontier Intelligence to Revolutionize Chip Design
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We just buried an ASIC design that was nearly finished. Reason: There was a deviation that would've needed a mask change, but because of AI chip demand, the manufacturer wanted so much money for it, that we said screw it.
So we now have AI powered chip design tools that make chip design cheaper, but because of AI, chip manufacturing has become so expensive, that we can't afford it anymore.
Nice.
From an investment perspective, I think chip fabs TSMC, Intel, and Samsung will benefit from better AI chip design tools.
If AI made it 100x faster and cheaper to build software, you suddenly have an explosion of software that need to be hosted. So companies like AWS/iOS App Store/cloud companies benefit.
If AI makes designing chips 100x faster and cheaper, you will have an explosion of custom chips for all sorts of applications. These chips still need to be physically made at TSMC, Intel, or Samsung.
Apple says it takes 3-4 years to design each Apple Silicon generation.[0] So the M6 was being designed in 2022-2023 already. Reports are that it costs hundreds of millions to a billion to design a cutting edge chip from scratch to finish.[0]
The cool thing is that we'll have niche ASIC chips for accelerating special applications that previously didn't have big of a market for someone to make a profit on. This is the same thing with software today. It's much easier to build custom software for a small niche and be profitable today than in 2022.
Maybe some day, a kid in his garage can just tell an AI to design a custom chip, send it to TSMC, and get the chip in the mail in a few weeks.
And given that Moore's Law is essentially dead in terms of density scaling, having an AI to automatically optimize the hell out of design and squeeze as much performance as possible out of the transistors could help us have a few more years of nice performance increase.
[0]https://fireflies.ai/blog/johny-srouji-and-john-ternus-inter...
[1]https://www.granitefirm.com/blog/us/2023/04/29/cost-of-chip-...
Only tangentially related but many many years ago, I spent a good chunk of a summer internship at synopsys fixing gcc warnings in one of their products. The codebase was huge, with many parts of it more than a decade old at that point. I learned a lot about obscure corners of C. These days a frontier model could do that job in a few days (or maybe just one day if the build and testing process has been sped up - it took several hours on a dedicated cluster back then).
> I see you are using Cadence IP in your project, unfortunately this is not allowed per the terms and conditions and you will be reported to the authorities
Also : create proprietary locked down eda->no data to train models->models suck at it->reach out to ai lab to rl on it -> expect users to pay for eda and the model.
„The joint service offering will provide the bundled compute, model, and licenses, while ensuring customer-specific design data is protected.“
I am not sure if Nvidia want to send their chip designs to OpenAI.
Give us more open source EDA tools, not more hyped up EDA vendors.
A question to those active in chip design industry: Are formal methods and formally proving a design more prevalent and normal in this industry compared to general software development?
Like for a Arm microcontroller design, do engineers thoroughly test and formally prove the correct functionality of every component? If that's the case, why silicon errata is a thing?
Having written a lot of Tcl glue for PrimeTime and ICC, the hard part was never writing the constraints, it was knowing which timing violation to actually believe.
Apparently SNPS share price gone up a little bit because of this. However, the rise didn't compensate their loss over the years. I keep wondering why EDA companies didn't get the hype like AI labs and Chip design companies.
I don't know how much of a difference this makes in practice. Creating the photomasks and proving the resulting silicon is still the predominant bottleneck in chip design.
If you have a flaw in the RTL and need to do a respin it can add 3+ months to the lead time of a new product. Allowing GPT to iterate through this kind of cycle seems economically infeasible unless you have an enormous amount of spare EUV capacity (you don't).
ChatGPT, pretend you are a grizzled hardware engineer and make me a 1nm chip for the iPhone.
Something like JLCPCB but for chips would be revolutionary.
Can't wait for vibe coded SoCs.
Prompt injection in hardware! What could possibly go wrong?
Astra is amazing with open PDKs. ;)
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It's hard to believe these probabilistic language model can replace deterministic, precise control of matter needed in hardware design.